The invention disclosed herein relates generally to keyboard data input assemblies, and more particularly to such assemblies including circuitry for minimizing the required number of interconnections with a microprocessor or other apparatus with which a keyboard is used. The invention also includes a keyboard circuit board layout for use in such assemblies.
Keyboards having a plurality of key switch devices are particularly well suited for use in data processing systems. In general, the number of signals which must pass between a keyboard and associated data processing system is the same as the number of switch devices. Each of these signals can be carried over a separate interconnection. However, particularly in large keyboards, the resulting number of interconnections may be prohibitive.
One technique which can be used to reduce the number of interconnections involves the use of logic gates for providing an encoded signal indicative of actuated switches. U.S. Pat. No. 3,778,815 issued to C. Wright on Dec. 11, 1973 discloses a keyboard encoder in which logic gates respond to a portion of a group of timing pulses by applying binary signals through an actuated key switch in one direction. The logic gates also respond to the remaining timing pulses by applying binary signals through the switch in the opposite direction. After passing through a switch, a signal is gated through one of two logic circuits under the control of the same timing pulse employed to produce the signal. In this arrangement, depending on the relative portion of the logic gates located at the keyboard, the number of interconnections with an associated data processing system can be substantially reduced.
Another technique commonly used for reducing the required number of keyboard interconnections involves connecting the key switch devices between column and row conductors in a conductor matrix. When actuated, a switch device provides continuity between the column and row conductors associated therewith. In operation, enabling signals from the data processing system may be sequentially coupled to each column (or row) conductor for scanning the keyboard for depressed keys. A depressed key is sensed when the enabling signal from its column (or row) conductor is present on its row (or column) conductor. In such a system having J columns and K rows, the data processing system must provide J (or K) enabling signals for the columns, and monitor K (or J) row conductors. As a result, J +K signals are required to pass between the keyboard and the data processing system. This generally requires a like number (J +K) of interconnections between the keyboard and data processing system in contrast to J.times.K interconnections if each switch is connected separately.
A variety of techniques have been employed to further simplify matrix keyboard apparatus and reduce the number of interconnections between such keyboards and data processing systems associated therewith. For example, U.S. Pat. No. 4,148,017 issued to N. Tomisawa on Apr. 3, 1979 discloses a circuit for detecting key switch operation in a matrix keyboard wherein the array of switches is divided into blocks. First terminals of switches in a block are commonly connected and second terminals of corresponding switches in all blocks are commonly connected. A signal is transmitted to all column conductors and transferred through an actuated switch to a block conductor of the associated block. This signal is sent back through the block conductor and appears on the column conductor of the actuated switch. The position of the actuated switch is determined by detecting the column on which the signal appears.
U.S. Pat. No. 4,186,385 issued to S. Nagashima on Jan. 29, 1980 discloses a matrix keyboard assembly wherein the switches are connected in two groups such that the first group is coupled to first inputs of AND gates in a first group of such gates and the second group is coupled to first inputs of AND gates in a second group of such gates. Second inputs of the AND gates in the first and second groups are individually connected together and coupled to a separate switch from each of the first and second groups of switches so that actuation of a switch will coincidently energize both inputs of a corresponding gate.
U.S. Pat. No. 4,222,038 issued to R. Magerl on Sept. 9, 1980 discloses matrix keyboard input circuitry in which the number of interconnections is reduced by providing a counter/decoder at the keyboard which is operated in synchronism with a register in the data processing system. The counter/decoder is, thus, caused to sequentially enable columns in the keyboard matrix by means of a clock signal which is supplied over one conductor. The states of the rows (i.e., whether a row is coupled to an enabled column through a depressed key) is transmitted back to the data processing system over data conductors.
Each of the previously described techniques can be used to reduce the number of interconnections between keyboard apparatus and a data processing system. The reductions are accomplished by means of circuit elements and devices such as logic gates and counter/decoders which are not overly complex. However, there is a continuing demand to further reduce the required number of interconnections and to further simplify the circuitry used to achieve such reductions.
The applicant has devised a matrix keyboard with interface circuitry comprising only a small number of diodes which permits the same set of interconnections to carry both enabling signals to the keyboard and readout signals from the keyboard. Accordingly, the number of keyboard/data processing system interconnections is minimized and the use of minimum interconnections is made possible with exceedingly simple interface circuitry.